Developing FPGA-accelerated cloud applications with SDAccel: Theory
- Offered byCoursera
- Public/Government Institute
Developing FPGA-accelerated cloud applications with SDAccel: Theory at Coursera Overview
Duration | 19 hours |
Total fee | Free |
Mode of learning | Online |
Difficulty level | Intermediate |
Official Website | Explore Free Course  |
Credential | Certificate |
- Overview
- Highlights
- Course Details
- Curriculum
Developing FPGA-accelerated cloud applications with SDAccel: Theory at Coursera Highlights
- Shareable Certificate Earn a Certificate upon completion
- 100% online Start instantly and learn at your own schedule.
- Flexible deadlines Reset deadlines in accordance to your schedule.
- Intermediate Level This course is aimed at students with prior programming experience and a desire to understand computation approaches to problem solving.
- Approx. 19 hours to complete
- English Subtitles: English
Developing FPGA-accelerated cloud applications with SDAccel: Theory at Coursera Course details
- This course is for anyone passionate in learning how to develop FPGA-accelerated applications with SDAccel!
- We are entering in an era in which technology progress induces paradigm shifts in computing!
- As a tradeoff between the two extreme characteristics of GPP and ASIC, we can find a new concept, a new idea of computing... the reconfigurable computing, which has combined the advantages of both the previous worlds. Within this context, we can say that reconfigurable computing will widely, pervasively, and gradually impact human lives. Hence, it is time that we focus on how reconfigurable computing and reconfigurable system design techniques are to be utilised for building applications.
- One one hand reconfigurable computing can have better performance with respect to a software implementation but paying this in terms of time to implement. On the other hand a reconfigurable device can be used to design a system without requiring the same design time and complexity compared to a full custom solution but being beaten in terms of performance.
- Within this context, the Xilinx SDx tools, including the SDAccel environment, the SDSoC environment, and Vivado HLS, provide an out-of-the-box experience for system programmers looking to partition elements of a software application to run in an FPGA-based hardware element, and having that hardware work seamlessly with the rest of the application running in a processor or embedded processor.
- The out-of-the-box experience will provide interesting and, let us say, ?good enough? results for many applications.
- However, this may not be true for you, you may be looking for better performance, data throughput, reduced latency, or to reduce the resources usage... This course is focusing exactly on this. After introducing you to the FPGAs we are going to dig more into the details on how to use Xilinx SDAccel providing you also with working examples on how to optimize the hardware logic to obtain the best of of your hardware implementations. In this case, certain attributes, directives, or pragmas, can be used to direct the compilation and synthesis of the hardware kernel, or to optimise the function of the data mover operating between the processor and the hardware logic.
- Furthermore, In this course we are going to focus on distributed, heterogeneous infrastructures, presenting how to bring your solutions to life by using the Amazon EC2 F1 instances.
Developing FPGA-accelerated cloud applications with SDAccel: Theory at Coursera Curriculum
Familizarize youself with FPGA technologies
Reconfigurable Computing and FPGA technologies
FPGA-based systems and reconfiguration
Programmable System-on-Multiple Chips
Programmable System-on-Chips
FPGAs main building blocks
How to program an FPGA: bitstream and configuration
How to program an FPGA: system description and physical design
CAD Tools for FPGA-based systems design
An introuction to the SDx development environment
QUIZ 1
QUIZ 2
A bird's eye view on SDAccel
Hardware Design Flow
An introduction to SDAccel and the OpenCL-based flow
OpenCL computational model: global and local sizes
Not only OpenCL! The Rationale behind the RTL and C flows
SDAccel memory model
SDAccel "emulations"
SDAccel runtime
SDAccel Environment Programmers Guide
QUIZ 3
On how to optmize your system
Introduction
FPGA Parallelism vs Processor Architecture 1/2
FPGA Parallelism vs Processor Architecture 2/2
Scheduling, Pipelining, and Dataflow
Application Optimization Flow
SDAccel Environment Profiling and Optimisation Guide
QUIZ 4
A bird's eye view on SDAccel optimizations
Interface optimizations: Overall context and an overview of a typical target architecture
Interface optimizations: a first example
Burst data transfer
Using full AXI data width
Using multiple memory banks
SDAccel Environment Profiling and Optimisation Guide
Sources Codes
QUIZ 5
Other optimizations
Kernel optimization: loop unrolling 1/2
Kernel optimization: loop unrolling 2/2
Kernel optimization: loop pipelining
Kernel optimization: array partitioning 1/2
Kernel optimization: array partitioning 2/2
Host optimizations
SDAccel Environment Profiling and Optimisation Guide
Source Codes
QUIZ 6
FPGA-enable cloud infrastructures
An introduction to SDAccel and the AWS EC2 F1 instances
Closing remarks and future directions
A Scalable FPGA Design for Cloud N-Body Simulation
QUIZ 7
Other courses offered by Coursera
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