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Advanced Armv8-M Features 

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Advanced Armv8-M Features


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Advanced Armv8-M Features

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Advanced Armv8-M Features
Course details

Skills you will learn
More about this course
  • The final course covers more advanced and optional features that might be configured in a Cortex-M system
  • These features could help with particular project requirements such as security and performance

Advanced Armv8-M Features

Course Introduction

Course introduction


The Exclusive Monitor

Examples of lock(), unlock() and Multi-thread Mutex

Non-coherent Multiprocessor - Part 1

Non-coherent Multiprocessor - Part 2

Examples of Multiprocessor Mutex

Memory Ordering

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Cache Management

What is a Cache?

How is a Cache Accessed?

How is a Cache Populated?

Direct Mapped Cache

Set Associative Cache

Cache Terminology

Cortex-M7 and Cortex-M55 Caches

Level 2 Caches

Data Cache Policies, caching and memory attributes - Part 1

Data Cache Policies, Caching and Memory Attributes - Part 2

Cache Coherency & L1 Memory System Buffers

Point of Coherency and Point of Unification

Cache Maintenance Operations

Initializing and Enabling L1 Caches

Cache Discovery Code

What Should I Cache?

Non-deterministic Cache Behavior

Cache Optimizations

Error Correcting Code for Caches

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Cache Management

DSP Extension

DSP overview - Part 1

DSP overview - Part 2

DSP extension instruction set - Part 1

DSP Extension instruction set - Part 2

DSP tools and library support

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DSP extensive

Floating-point Extension

Floating-point Extension Overview

Data-processing Floating-point Registers

Floating-point Status and Control Register

Floating-point Default Status Control Register &Floating-point Context Control R

Enabling the FPU

Floating-point Instructions

Floating-point Exceptions & Exception Handling

Floating-point Context Control

Lazy Context Save

Interaction with Security Extension

Floating-point Extension Reference Material

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Floating Point Extension

SysTick Timer Extension

The SysTick Timer

SysTick Operation

Using CMSIS for SysTick

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SysTick Timer Extension

Security Extension (TrustZone for Arm8-M)

Armv8-M Security Extension Overview

Memory Security

Secure and Non-secure Views of the System Control Space

SAU Configuration

Function Calls

Calling Non-secure Code from Secure Code

Calling Secure Code from Non-secure Code

Toolchain Support

Interrupts and Exceptions

Taking an Exception

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Security Extension (TrustZone for Armv8-M)

PACBTI Extension

Introduction to PAC-BTI Extension - Part 1

Introduction to PAC-BTI Extension - Part 2

Pointer Authentication Code (PAC)

PAC Generation & Cryptographic Keys

PAC Operations

Pointer Authentication in Use

Branch Target Identification (BTI)

BTI Across Security States

BTI with PAC and with Implied Branches

Debugging PAC and BTI

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PACBTI Extension

M-profile Vector Extension (MVE)

MVE Overview

Vector Extension Operation

Vector Register File

MVE Features: Lanes

MVE Features: Beats

Exception State

Loop Tail Predication -Describe why Arm introduced MVE to the Armv8.1-M architecture

VPT Predication -Summarize the main features of MVE

Interleaving and de-interleaving Loads and Stores - Part 1

Interleaving and de-interleaving Loads and Stores - Part 2

How to use MVE

CMSIS-DSP and CMSIS-NN Libraries

Automatic Vectorization

Intrinsics - Part 1

Intrinsics - Part 2


MVE Reference Material

MVE Challenge

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M-profile Vector Extension (MVE)

Advanced Armv8-M Features
Admission Process

    Important Dates

    May 25, 2024
    Course Commencement Date

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