Developing FPGA-accelerated cloud applications with SDAccel: Practice
- Offered byCoursera
- Public/Government Institute
Developing FPGA-accelerated cloud applications with SDAccel: Practice at Coursera Overview
Duration | 13 hours |
Total fee | Free |
Mode of learning | Online |
Difficulty level | Intermediate |
Official Website | Explore Free Course  |
Credential | Certificate |
Developing FPGA-accelerated cloud applications with SDAccel: Practice at Coursera Highlights
- Shareable Certificate Earn a Certificate upon completion
- 100% online Start instantly and learn at your own schedule.
- Flexible deadlines Reset deadlines in accordance to your schedule.
- Intermediate Level
- Approx. 13 hours to complete
- English Subtitles: English
Developing FPGA-accelerated cloud applications with SDAccel: Practice at Coursera Course details
- This course is for anyone passionate about learning how to develop FPGA-accelerated applications with SDAccel!
- The more general purpose you are, the more flexible you are and the more kinds of programs and algorithms you can execute on your underlying computing infrastructure. All of this is terrific, but there is no free food and this is happening, quite often, by losing in efficiency.
- This course will present several scenarios where the workloads require more performance than can be obtained even by using the fastest CPUs. This scenario is turning cloud and data center architectures toward accelerated computing. Within this course, we are going to show you how to gain benefits by using Xilinx SDAccel to program Amazon EC2 F1 instances. We are going to do this through a working example of an algorithm used in computational biology.
- The huge amount of data the algorithms need to process and their complexity raised the problem of increasing the amount of computational power needed to perform the computation. In this scenario, hardware accelerators revealed to be effective in achieving a speed-up in the computation while, at the same time, saving power consumption. Among the algorithms used in computational biology, the Smith-Waterman algorithm is a dynamic programming algorithm, guaranteed to find the optimal local alignment between two strings that could be nucleotides or proteins. In the following classes, we present an analysis and successive FPGA-based hardware acceleration of the Smith-Waterman algorithm used to perform pairwise alignment of DNA sequences.
- Within this context, this course is focusing on distributed, heterogeneous cloud infrastructures, providing you details on how to use Xilinx SDAccel, through working examples, to bring your solutions to life by using the Amazon EC2 F1 instances.
Developing FPGA-accelerated cloud applications with SDAccel: Practice at Coursera Curriculum
Reconfigurable cloud infrastructure
Course introduction
An overview of cloud infrastructure
Cloud Computing: few definitions
Reconfigurable acceleration in the Cloud
Reconfigurable acceleration in the Cloud: Intel FPGA-based solutions
Reconfigurable acceleration in the Cloud: Xilinx FPGA-based solutions
Reconfigurable acceleration in the Cloud: from the past, to the future
An introduction to the AWS EC2 F1 instances
QUIZ 1
QUIZ 2
QUIZ 3
On how to accelerate the cloud with SDAccel
Applicative domains and Victor's story
F1: instances and FPGA description
How FPGA Acceleration Works on AWS
AWS F1 Platform Model
Creating Kernels from RTL IP, C/C++, OpenCL
Compiling the Platform
Creating an Amazon FPGA Image
Developing and Executing a Host Application on F1
Start Accelerating
QUIZ 4
QUIZ 5
QUIZ 6
Summing things up: the Smith-Waterman algorithm
Problem description
Algorithm and code analysis
Roofline model 1/2
Roofline model 2/2
Code profiling
Static Code Analysis 1/2
Static Code Analysis 2/2
Performance Prediction via Roofline Model
SDAccel Environment Profiling and Optimisation Guide
QUIZ 7
The Smith-Waterman example in details
A first implementation 1/3
A first implementation 2/3
A first implementation 3/3
Parallelism in the Smith-Waterman Algorithm
Systolic Array Architecture 1/2
Systolic Array Architecture 2/2
Input Compression
Shift Register
Dual Physical Ports
Smith-Waterman accelerated on the Amazon EC2 F1 instances 1/3
Smith-Waterman accelerated on the Amazon EC2 F1 instances 2/3
Smith-Waterman accelerated on the Amazon EC2 F1 instances 3/3
Sources Codes
Source Codes
QUIZ 8
QUIZ 9
Closing remarks and future directions
Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL
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