IIT Madras Hosts 2nd Digital India RISC-V Symposium, Driving Innovation in Open-Source Chip Design

IIT Madras hosted the 2nd Digital India RISC-V (DIR-V) Symposium, fostering advancements in India's indigenous chip design ecosystem and strengthening the nation’s semiconductor capabilities.

IIT Madras Hosts 2nd Digital India RISC-V Symposium

Indian Institute of Technology (IIT) Madras, in collaboration with the Union Ministry of Electronics and Information Technology (MeitY), RISC-V International, and industry leaders, is hosting the Second Digital India RISC-V (DIR-V) Symposium. As a key platform for advancing India's self-reliance in semiconductor technology, DIR-V Symposium 2025 aligns with national initiatives like ‘Digital India,’ ‘Make in India,’ and the ‘India Semiconductor Mission.’

Introducing the Chief Guest and Former Union Minister of State Rajeev Chandrasekhar, Prof. V. Kamakoti, Director, IIT Madras, said, “He is the man behind DIR-V. He coined the word ‘Digital India RISC-V’ and was kind enough to make a National announcement. India now has a National Instruction Set Architecture (ISA), which we owe to Shri Rajeev Chandrasekhar.”

Delivering the Chief Guest Address, Shri Rajeev Chandrasekhar, former Union Minister of State for Electronics and Information Technology, said, “This is certainly the most exciting period in the history of technology. The opportunities today are tremendous in terms of almost re-scripting the landscape of technology as we knew it all these years. Indian entrepreneurs, brands and companies have traditionally lagged, for almost 25 years, in the areas of semiconductors and electronics. We had no notable architecture, systems, solution, component or device that we have done over the last two-and-a-half decades. Effectively, we were an innovation economy that worked off of architectures, platforms and systems that were designed and built elsewhere and we created software stacks and layers of applications around that.”

Addressing the symposium earlier, Prof. V. Kamakoti added, “RISC-V, being an open-source, extensible domain specific Instruction Set Architecture (ISA), has a great promise for us to design novel normative architectures and make it available to the startup industry who can in turn, customize them and make very efficient and effective domain specific SoCs (System-on-Chips).”

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