

M.Tech. in VLSI and Embedded Systems Design
- Public/Government Institute
- Estd. 1981
M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Overview
Shri Guru Gobind Singhji Institute of Engineering and Technology offers M.Tech. in VLSI and Embedded Systems Design programme at the PG level in a Full Time mode. It is a 2 years course with a seat capacity of 18. The total tuition fee for this course is INR 1,86,484. Check the Shri Guru Gobind Singhji Institute of Engineering and Technology courses in this space:
Total Tuition Fees | ₹1.86 Lakh Get Fees details |
Duration | 2 years |
Course Level | PG Degree |
Mode of Course | Full Time |
Official Website | Go to Website |
Seat breakup | 18 |
Type of University | Public/Government,Autonomous |
M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Fees
Shri Guru Gobind Singhji Institute of Engineering and Technology M.Tech. in VLSI and Embedded Systems Design fees is consists of several elements, such as tuition fees, one-time charges, registration fees, exam fees, and other expenses. Candidates might have to pay additional charges depending on the breakdown of the fee for the latest year. The total tuition fee for M.Tech. in VLSI and Embedded Systems Design at Shri Guru Gobind Singhji Institute of Engineering and Technology amounts to INR 1,86,484. Below is a detailed breakdown of the M.Tech. in VLSI and Embedded Systems Design fee structure at Shri Guru Gobind Singhji Institute of Engineering and Technology:
| Fee components | Amount (2 years) |
|---|---|
Additionally Amaratya LIC Yojana fee is INR 234.
SC/ST first year fee is INR 22476 | ₹ 1.86 Lakh |
₹ 1.86 Lakh |
M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Frequently Asked Questions
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M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Placements
| Particulars | Statistics (2023) |
|---|---|
| Median Salary | INR 4.00 Lakh |
M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Entry Requirements
M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Admission Process
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M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Cutoffs
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The last date to apply for the Common Entrance Test (IPU CET) 2024 for Guru Gobind Singh Indraprastha University (GGSIPU) was April 15, 2024. The IPU CET is usually held once a year for admission to various undergraduate and postgraduate programs at GGSIPU.
Here are some other admission dates for GGSIPU:
CLAT 2025
The last date to apply for admission to the 5-year Integrated LLB (UG) and one-year LLM (PG) courses is October 22, 2024. The exam will be held on December 1, 2024.
GATE 2025
The registration process for admission to the MTech course with late fee is closed. The exam will be held on February 1, 2, 15, and 16,
2025.
| Courses | Eligibility |
|---|---|
| B.E. / B.Tech | Candidate must have completed Diploma Course in Engineering and Technology in relevant stream with minimum 45% marks (40% marks in case of candidates of Backward class categories and Persons with Disability belonging to Maharashtra State only) from an All India Council for Technical Education or Central or State Government approved Institution or its equivalent. OR Candidate must have completed B.Sc. from UGC/ Association of Indian Universities recognized University with at least 45% marks (40% in case of candidates of Backward class categories and Persons with Disability belonging to Maharashtra State only) and passed 10+2 with Mathematics as a subject. |
| Ph.D. | Candidate must have Master's degree in relevant stream from a recognized University are eligible to apply. |
| M.E./M.Tech | Sponsored candidate must have minimum of two years of full time work experience in a registered firm/ company/ industry/ educational and/ or research institute/ any Government Department or Government Autonomous Organization in the relevant field in which admission is being sought. |
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M.Tech. in VLSI and Embedded Systems Design at SGGSIE&T Contact Information
Vishnupuri
Nanded Maharashtra
Nanded ( Maharashtra)
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