B.Tech. in ECE (Chip Design) in collaboration with L&T
- Private University
- Estd. 2004
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Overview
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Manav Rachna University offers a 4 years B.Tech. in ECE (Chip Design) in collaboration with L&T course at the UG level. Manav Rachna University B.Tech. in ECE (Chip Design) in collaboration with L&T admission is based on entry requirements - 55.0% in 12th. The total tuition fee for this course is INR 1026000 for entire duration of the course. Check other courses of Manav Rachna University B.E. / B.Tech.
Total Tuition Fees | ₹10.26 Lakh Get Fees details |
Duration | 4 years |
Course Level | UG Degree |
Mode of Course | Full Time |
Official Website | Go to Website  |
Type of University | Private |
B.Tech. in ECE (Chip Design) in collaboration with L&T
Table of contents
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Fees
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
| Fee components | Amount (4 years) |
|---|---|
The fees might include components other than tuition fees. | ₹ 10.26 Lakh |
One time fee includes Life Time Alumni Membership Fee | ₹ 3,000 |
₹ 5.18 Lakh | |
₹ 15.47 Lakh |
These are based on information available on various sources. Latest values may differ.View scholarships
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Frequently Asked Questions
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
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B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Entry Requirements
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
General
Requirements for 12th grade
- 55%
- Read moreCandidates must have passed 10+2 examination with minimum mentioned marks aggregate in Physics, Mathematics, English & Chemistry/ Computer Science/ Biology / Biotechnology and also with at least mentioned marks in aggregate in 5 subjects. The eligibility shall be determined on the basis of percentage of aggregate marks in English, Physics & Mathematics and One subject out of the given list as per Note-A and One subject with the highest score out of the remaining subjects.
CUET
JEE Main
SAT India
mySATHI
MRNAT
Other eligibility criteria
45% marks in 3-year Diploma in Engineering in any branch/discipline from State Board of Technical Education or Equivalent Examination
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Admission Process
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Important Dates
ALL
COURSE
MRNAT
SAT INDIA
JEE MAIN
CUET
Sep 12, 2026
SAT India Exam (September) Attempt
Oct 3, 2026
SAT India Exam (October) Attempt
Oct 31 - Nov 27, 2026
JEE Main 2027 Registration Session 1Tentative
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Contact Information
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Address
Sector – 43, Aravalli Hills, Delhi – Surajkund Road
Faridabad ( Haryana)
Phone
01294268500
(For general query)
911294259000
(For admission query)
Go to College Website ->
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