

B.Tech. in ECE (Chip Design) in collaboration with L&T
- Private University
- Estd. 2004
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Overview
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Manav Rachna University offers a 4 years B.Tech. in ECE (Chip Design) in collaboration with L&T course at the UG level. To get admitted to Manav Rachna University B.Tech. in ECE (Chip Design) in collaboration with L&T course, applicants must meet the entry requirements - 55.0% in 12th. Manav Rachna University The total tuition fee for this course is INR 1026000 for the entire duration of the course. Apart from the tuition fee, students are also required to pay a one-time fee of INR 3000. To learn more about other courses offered under B.E. / B.Tech at Manav Rachna University, please visit.
Total Tuition Fees | ₹10.26 Lakh Get Fees details |
Duration | 4 years |
Course Level | UG Degree |
Mode of Course | Full Time |
Official Website | Go to Website |
Type of University | Private |
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Fees
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
| Fee components | Amount (4 years) |
|---|---|
The fees might include components other than tuition fees. | ₹ 10.26 Lakh |
One time fee includes Life Time Alumni Membership Fee | ₹ 3,000 |
₹ 10.29 Lakh |
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Frequently Asked Questions
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
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at Manav Rachna University
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Entry Requirements
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
General
CUET
JEE Main
SAT
SAT India
MRNAT
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Admission Process
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Important Dates
ALL
COURSE
MRNAT
SAT INDIA
JEE MAIN
CUET
Jul 22 - Aug 18, 2026
JEE Main CSAB special counselling
Aug 22, 2026
SAT India Exam (August) Attempt
Sep 12, 2026
SAT India Exam (September) Attempt
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B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Contact Information
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Address
Sector – 43, Aravalli Hills, Delhi – Surajkund Road
Faridabad ( Haryana)
Phone
01294268500
(For general query)
911294259000
(For admission query)
Go to College Website ->
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