B.Tech. in ECE (Chip Design) in collaboration with L&T
- Private University
- Estd. 2004
B.Tech. in ECE (Chip Design) in collaboration with L&T
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Overview
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Manav Rachna University's B.Tech. in ECE (Chip Design) in collaboration with L&T is a 4 years course offered at the UG level. To be eligible for this course, students must have 55.0% in 12th. The total tuition fee for B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University is INR 1026000. Additionally, there is a one-time admission fee of INR 3000 that students are required to pay. Discover other available courses under B.E. / B.Tech at Manav Rachna University.
Total Tuition Fees | ₹10.26 Lakh Get Fees details |
Duration | 4 years |
Course Level | UG Degree |
Mode of Course | Full Time |
Official Website | Go to Website  |
Type of University | Private |
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Fees
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
| Fee components | Amount (4 years) |
|---|---|
The fees might include components other than tuition fees. | ₹ 10.26 Lakh |
One time fee includes Life Time Alumni Membership Fee | ₹ 3,000 |
₹ 10.29 Lakh |
These are based on information available on various sources. Latest values may differ.View scholarships
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Frequently Asked Questions
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
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B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Entry Requirements
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
General
Requirements for 12th grade
- 55%
- Read moreStudent must have done 10+2 with at least 55% marks in aggregate in Physics, Mathematics, English, and one of the following: Chemistry, Computer Science, Biology, or Biotechnology. And also the aggregate of top five subjects English, Physics, Mathematics, One subject from the list above, and one subject with the top marks from the remaining subjects.
CUET
JEE Main
SAT
mySATHI
MRNAT
Other eligibility criteria
45% marks in 3-year Diploma in Engineering in any branch/discipline from State Board of Technical Education or Equivalent Examination
B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Admission Process
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Important Dates
ALL
MRNAT
JEE MAIN
CUET
Jul 11, 2026
CUET UG 2026 ResultTentative
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B.Tech. in ECE (Chip Design) in collaboration with L&T
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B.Tech. in ECE (Chip Design) in collaboration with L&T at Manav Rachna University Contact Information
B.Tech. in ECE (Chip Design) in collaboration with L&T
at Manav Rachna University
Address
Sector – 43, Aravalli Hills, Delhi – Surajkund Road
Faridabad ( Haryana)
Phone
01294268500
(For general query)
911294259000
(For admission query)
Go to College Website ->
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