
M.E. in VLSI and Embedded System Design
- Private Institute
- Estd. 2008
M.E. in VLSI and Embedded System Design at Sinhgad Institute of Technology and Science Overview
The M.E. in VLSI and Embedded System Design at SITS - Sinhgad Institute of Technology and Science is a top choice for students at the PG level. It spans a duration of 2 years. This course has a total tuition fee of INR 1,15,000 for the entire duration. Admission to the SITS - Sinhgad Institute of Technology and Science course is limited to 24 students. Explore other courses of SITS - Sinhgad Institute of Technology and Science M.E./M.Tech.
Total Tuition Fees | ₹1.15 Lakh Get Fees details |
Duration | 2 years |
Course Level | PG Degree |
Mode of Course | Full Time |
Official Website | Go to Website |
Seat breakup | 24 |
Type of University | Private |
M.E. in VLSI and Embedded System Design at Sinhgad Institute of Technology and Science Fees
The total SITS - Sinhgad Institute of Technology and Science M.E. in VLSI and Embedded System Design fee is made up of multiple components, including Tuition Fees, One-Time Fees, Registration Fees, Exam Fees, and other associated costs. In addition to the standard fees, students may incur extra charges specific to SITS - Sinhgad Institute of Technology and Science. The total tuition fee for the M.E. in VLSI and Embedded System Design program at SITS - Sinhgad Institute of Technology and Science is INR 1,15,000. For a detailed breakdown of the SITS - Sinhgad Institute of Technology and Science M.E. in VLSI and Embedded System Design fee breakup, please refer to the following information:
Fee components | Amount (2 years) |
---|---|
₹ 1.15 Lakh | |
₹ 1.15 Lakh |
M.E. in VLSI and Embedded System Design at Sinhgad Institute of Technology and Science Frequently Asked Questions

Candidates can check MHT CET provisional seat allotment by following the below steps:
Step 1: Visit the official website of the Maharashtra State Common Entrance Test Cell i.e., cetcell.mahacet.org.
Step 2: On the Home Page, select BE/ BTech from the undergraduate section
Step 3: On the screen, the portal for admission activity updates will appear
Step 4: Select the MHT CET CAP Provisional Seat Allotment Result from the page for a particular round
Step 5: Enter all of the required information to view the provisional allotment result for Round

Download exam sample paper
M.E. in VLSI and Embedded System Design at Sinhgad Institute of Technology and Science Entry Requirements
M.E. in VLSI and Embedded System Design at Sinhgad Institute of Technology and Science Admission Process
- Entrance TestEligible candidates need to appear for the EntranceTest conducted by the college. Candidates who have valid score in GATE exam are exempted from college level entrance exam.
- Final SelectionCandidates are selected based on EntranceTest/ GATE rank.
Important Dates
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Courses | Eligibility |
---|---|
M.E./M.Tech | Candidate must have completed Bachelor Degree in the relevant field from AICTE or Central or State Government approved institutions or equivalent, with above mentioned marks (at least 45% marks in case of candidates of Backward class categories and persons with disability belonging to Maharashtra State only). For sponsored candidates, candidate must have minimum of two years of fulltime work experience in a registered firm/ company/industry/ educational and/ or research institute/ any Government Department or Government Autonomous Organization in the relevant field in which admission is being sought. |
B.E. / B.Tech | Candidate who have passed Diploma in Engineering & Technology & obtained at least 45% marks (40% marks for Backward class, EWS & PWD candidates belonging to Maharashtra State only) can also apply. |


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M.E. in VLSI and Embedded System Design at Sinhgad Institute of Technology and Science Contact Information
Narhe Technical Campus,
49/1, Opp. Mumbai Bengaluru Westerly Bypass
Pune ( Maharashtra)
(For general query)
(For admission query)
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